This invention relates to the manufacture of thin-film field effect transistors, and in particular to a method of patterning the source and drain electrodes to have a desired alignment with the gate electrode.
In solid state electronic devices thin film field effect transistors (TFTs) are commonly used as switches. In particular, in imaging and display devices, a TFT is commonly associated with each pixel to enable a respective electrical signal to be coupled to or from each individual pixel. To maximize the active pixel area in an imager or display device, it is advantageous that the TFT be as small as possible. Further, the large number of pixels in an array require that the associated TFTs be relatively small so as to not require physically larger arrays. Additionally, array performance is improved as TFT size is decreased because total gate capacitance, gate to source capacitance, and gate to drain capacitance can be minimized.
The total gate capacitance should be small in order to reduce the total capacitance of the address line (e.g., a scan line) that control a row of TFTs in the imaging or display device. The charging time of the address line is controlled by the product of the line resistance and line capacitance. The total gate capacitance is added to the line capacitance in determining the address line charging time.
The gate to drain and gate to source capacitances, respectively, should be small to minimize the coupling capacitance between the input address line, which is connected to the gate, and imaging or display element connected to the source or drain.
A primary determinant of the gate to source and gate to drain capacitances is the overlap of the source and drain electrodes, respectively, over the gate electrode. Fabrication of small TFTs with the source and drain electrodes aligned over the gate electrode can be difficult. One reason is that photolithographic processes are commonly used to pattern the source and the drain electrode, and there is typically some positioning misalignment of about 2 microns or more that must be accounted for in device layout. This amount of misalignment requires that the regions where the gate overlaps the source and drain be made larger than otherwise required. These enlarged sizes to account for the misalignment result in increased gate to source and gate to drain capacitances as noted above.
Approaches to reducing this misalignment are found in U.S. Pat. No. 5,010,027, of G. Possin et al., and U.S. Pat. No. 5,156,986 of C. Wei et al., which are all assigned to the assignee of the present invention, and which are incorporated herein by reference.
One object of the present invention is to provide an improved fabrication process for TFTs having self-aligned source and drain electrodes.
Another object of the present invention is to provide a self-aligned lift-off method of fabricating a TFT that provides faster liftoff times.